The present invention pertains to a regulator circuit which regulates an output voltage to a desired voltage. More specifically, it pertains to a regulator circuit that functions to regulate an overcurrent.
FIG. 5 is an outlined circuit diagram showing an configuration of a conventional series regulator having an overcurrent regulator circuit.
In the series regulator shown in FIG. 5, negative output terminal of DC voltage source Vin is connected to a ground line, and positive output terminal is connected to terminal N1 of current detection resistor 3. The other terminal N2 of current detection resistor 3 is connected to the drain of n-type MOS transistor 1. Smoothing capacitor CL and current load IL are connected between source N3 of n-type MOS transistor 1 and the ground line.
In addition, resistors 2a and 2b for voltage detection are connected in series between source N3 of n-type MOS transistor 1 and the ground line, and midpoint N4 between them is connected to positive input terminal + of differential amplifier circuit 4a. Negative terminal xe2x88x92 of differential amplifier circuit 4a is connected to the ground line by way of the positive terminal of voltage source VR1 via its negative terminal. The difference in the voltage between said positive input terminal + and negative input terminal xe2x88x92 is amplified by differential amplifier circuit 4a and input into base N5 of npn transistor 4c. 
The emitter of npn transistor 4c is connected to the ground line, and the collector is connected to power supply line Vcc via constant-current circuit 4b as well as to base N6 of npn transistor 4d. The collector of npn transistor 4d is connected to power supply line Vcc, and the emitter is connected to the ground line via constant-current circuit 4e. Said emitter is also connected to gate N7 of n-type MOS transistor 1.
Terminal N2 of current detection resistor 3 is connected to negative input terminal xe2x88x92 of comparator 5a. Terminal N1 of current detection resistor 3 is connected to positive input terminal + of comparator 5a by way of the positive output terminal of voltage source VR2 via its negative output terminal. A high-level or a low-level voltage in accordance with the result of a comparison of the voltage levels of said positive input terminal + and negative input terminal xe2x88x92 is generated by comparator 5a and input into the gate of n-type MOS transistor 5b. Base N6 of npn transistor 4d is connected to the ground line via the drain source terminal of n-type MOS transistor 5b. 
In the series regulator with the aforementioned configuration, the error between the detected value of the output voltage and its target value is amplified by differential amplifier circuit 4a and fed back negatively to the gate of n-type MOS transistor 1 in order to regulate the output voltage supplied to current load IL.
For example, when the voltage at source N3 of n-type MOS transistor 1 increases, the voltage at node N4 where said voltage is divided by resistors 2a and 2b also increases. Accordingly, output voltage of differential amplifier circuit 4a also increases, and collector current of npn transistor 4c increases, so that base voltage of npn transistor 4d drops. Therefore, emitter voltage of npn transistor 4d drops, and gate voltage of n-type MOS transistor 1 drops. As the gate voltage drops, the current between the drain and the source of the n-type MOS transistor is lowered, and the voltage of source N3 drops.
Similarly, when the voltage of source N3 of n-type MOS transistor 1 drops, output voltage of differential amplifier circuit 4a drops, base voltage of npn transistor 4d increases, and gate voltage of n-type MOS transistor 1 increases, so that the voltage of source N3 also increases.
As described above, negative feedback is applied to the voltage of source N3 of n-type MOS transistor 1 in order for the voltage at node N4 and the voltage of voltage source VR1 to become almost equal.
On the other hand, the circuit comprising current detection resistor 3, voltage source VR2, comparator 5a, and n-type MOS transistor 5b is a circuit for regulating overcurrent, and it shuts off n-type MOS transistor 1 when the current in current detection transistor 3 has exceeded a fixed level.
When the current in current detection resistor 3 is sufficiently low, and the difference in the potential between terminal N1 and terminal N2 is smaller than the difference in the potential related to voltage source VR2, the voltage of positive input terminal + of comparator 5a is lower than that of negative input terminal xe2x88x92. Therefore, the output of comparator 5a becomes low-level, and n-type MOS transistor 5b is turned off.
When the current in current detection resistor 3 increases, and the difference in the potential between terminal N1 and terminal N2 becomes greater than the potential related to voltage source VR2, the voltage of positive input terminal + of comparator 5a becomes higher than that of negative input terminal xe2x88x92, and the output of comparator 5a becomes high-level. As a result, n-type MOS transistor 5b is turned on, and the base voltage of npn transistor 4d drops to that of the ground line. Accordingly, the gate voltage of n-type MOS transistor 1 also drops to that of the ground line, and n-type MOS transistor 1 is turned off.
FIG. 6 is a diagram showing the changes in output voltage when the overcurrent regulating function of the series regulator in FIG. 5 is activated.
FIG. 6A shows an example of a simulated waveform of the current in current load IL, wherein the vertical axis represents load current level, and the horizontal axis represents time. In addition, FIG. 6B shows an example of a simulated waveform of the output voltage supplied to current load IL, wherein the vertical axis represents output voltage level, and the horizontal axis represents time.
As shown by the output voltage waveform in FIG. 6B, when the current in current load IL is increased from 0 A to 5 A to activate the overcurrent regulating function, the series regulator falls into an oscillating condition in which the output voltage vibrates between 0V and 900 mV repeatedly if the output voltage is set at 0.9V.
In other words, if the potential of gate N7 of n-type MOS transistor 1 drops to that of the ground line due to the overcurrent regulating function while under said oscillating condition, n-type MOS transistor is turned off, and the voltage of current detection resistor 3 drops. When the overcurrent regulating function is cancelled as a result, the output voltage starts increasing again, and the output current increases until the overcurrent regulating function is activated. As described above, in the case of the series regulator shown in FIG. 5, the overcurrent regulating function and the normal voltage control are repeated, resulting in the oscillation shown in FIG. 6B.
Once the voltage oscillation shown in FIG. 6B occurs, those circuits supplied with said voltage may start operating abnormally. In addition, a large pulse-like current flows into smoothing condenser CL, resulting in a problem of deteriorated condenser characteristics.
The present invention was formulated in light of said situation, and its objective is to present a regulator circuit capable of preventing output voltage oscillation when the overcurrent regulating function is activated.
In order to achieve the aforementioned goal, the regulator circuit of the present invention has a voltage output circuit which outputs a voltage in accordance with the level of a voltage control signal input, a voltage detection circuit which outputs a voltage detection signal of the level in accordance with the output voltage of the aforementioned voltage output circuit, a voltage control signal output circuit which selects either a first voltage setting signal input or a second voltage setting signal of a prescribed level according to the levels of the signals and outputs the aforementioned voltage control signal in accordance with the difference in level between said voltage setting signal and the aforementioned voltage detection signal, an overcurrent detection circuit which detects whether the output current level of the aforementioned voltage output circuit is in excess of a prescribed overcurrent level or not, and a voltage setting signal output circuit which sets the level of the aforementioned first voltage setting signal to a first level not selected by the aforementioned voltage control signal output circuit when no overcurrent is detected by the aforementioned overcurrent detection circuit and sets the level of the aforementioned first voltage setting signal to a second level to be selected by the aforementioned voltage control signal output circuit when an overcurrent is detected.
Ideally, when the aforementioned voltage setting signal output circuit changes from the condition in which an overcurrent is detected by the aforementioned overcurrent detection circuit to the condition in which no overcurrent is detected, the aforementioned first voltage setting signal is changed from the aforementioned second level to the aforementioned first level at a prescribed speed.
In addition, ideally, the aforementioned overcurrent level when the aforementioned overcurrent detection circuit changes from the overcurrent condition to the non-overcurrent condition is lower than that when it changes from the non-overcurrent condition to the overcurrent condition.
In addition, the aforementioned voltage control signal output circuit may also have a first transistor which takes the aforementioned voltage detection signal as an input and supplies a voltage signal to a first node, a second transistor which takes the aforementioned first voltage setting signal as an input and supplies a voltage signal to a second node, a third transistor which takes the aforementioned second voltage detection signal as an input and is connected in parallel to the aforementioned second transistor, a current source circuit which supplies current to the aforementioned first transistor and the aforementioned second or third transistor, a current-mirroring circuit which supplies equal current to the aforementioned first node and the aforementioned second node, and an output circuit which outputs the aforementioned voltage control signal in accordance with the difference in voltage between the aforementioned first node and the aforementioned second node.
In addition, the aforementioned voltage setting signal output circuit may also have a constant-current source, a capacitor which is charged by a current supplied from the aforementioned constant-current source, a transistor which becomes conductive to discharge the aforementioned capacitor in accordance with the detection result of the aforementioned overcurrent detection circuit, and a voltage source which applies a prescribed offset to the voltage charged by the aforementioned capacitor to generate the aforementioned first voltage setting signal.
Moreover, the aforementioned voltage output circuit may also be provided with a transistor having a voltage input terminal and a voltage output terminal and supplies an output voltage in accordance with the aforementioned voltage control signal input into its control terminal.